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NXP Semiconductors /LPC11Exx /CT16B1 /PWMC

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Interpret as PWMC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CT16BN_MAT0_IS_CONTR)PWMEN0 0 (CT16BN_MAT01_IS_CONT)PWMEN1 0 (CT16BN_MAT2_IS_CONTR)PWMEN2 0 (CT16BN_MAT3_IS_CONTR)PWMEN3 0RESERVED

PWMEN1=CT16BN_MAT01_IS_CONT, PWMEN0=CT16BN_MAT0_IS_CONTR, PWMEN3=CT16BN_MAT3_IS_CONTR, PWMEN2=CT16BN_MAT2_IS_CONTR

Description

PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0].

Fields

PWMEN0

PWM mode enable for channel0.

0 (CT16BN_MAT0_IS_CONTR): CT16Bn_MAT0 is controlled by EM0.

1 (PWM_MODE_IS_ENABLED_): PWM mode is enabled for CT16Bn_MAT0.
PWMEN1

PWM mode enable for channel1.

0 (CT16BN_MAT01_IS_CONT): CT16Bn_MAT01 is controlled by EM1.

1 (PWM_MODE_IS_ENABLED_): PWM mode is enabled for CT16Bn_MAT1.
PWMEN2

PWM mode enable for channel2.

0 (CT16BN_MAT2_IS_CONTR): CT16Bn_MAT2 is controlled by EM2.

1 (PWM_MODE_IS_ENABLED_): PWM mode is enabled for CT16Bn_MAT2.
PWMEN3

PWM mode enable for channel3.

0 (CT16BN_MAT3_IS_CONTR): CT16Bn_MAT3 is controlled by EM3.

1 (PWM_MODE_IS_ENABLED_): PWM mode is enabled for CT16Bn_MAT3.
RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data